Masataka Matsui

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— The two-dimensional discrete cosine transform (2-II DCT) has been widely recognized as a key processing unit for image data compressionldecompression. In this paper, the implementation of a 200 MHz 13.3 mm2 8 x 8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell,(More)
It is unclear whether the menstrual cycle affects the basics of performance, mainly task performance and cognitive functions. We examined menstrual cycle effects on VDT-based task performance, cognitive indices based on the signal-detection theory, and subjective ratings in questionnaires. We experimented in three phases: premenstrual, menstrual and(More)
An 80,000 transistor, low swing, 32~x~32-bit multiplier was fabricated in a standard 0.35&#956;m,<italic>V</italic><subscrpt>th</subscrpt>=0.5 V CMOS process and in a 0.35&#956;m, back-bias tunable, near-zero <italic>V</italic><subscrpt>th</subscrpt> process. While standard CMOS at<italic>V</italic><subscrpt>dd</subscrpt>=3.3 V runs at 136 MHz, the same(More)
— Interconnect delay is dominant in today's high speed VLSI circuits and there have been various works to resolve it [1],[2],[3]. A repeater insertion tool " RePertory " has been newly developed to solve the interconnect timing problem on a 300MHz 128-bit 2-way Superscalar Microprocessor. Because of its practical simple algorithm, the location of over 5700(More)
An extension interface for a configurable processor enabling implementation of an application specific programmable DSP is described. A DSP engine for mobile applications with 32-bit dual MAC architecture based on the extension was designed. The engine can also run separately as stand-alone processor decoupled with the configurable CPU core. A test chip was(More)