Masashi Kuwako

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Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the(More)
only on the causal relation of signal transitions with an average delay in-DeIa y-l nsens i tive Microprocessor MODERN DEVICE technology enables logic gates with a switching delay of only a few picosec-onds. But because no signal can reach further than 0.3 mm in 1 ps, the use of such fast switching devices presents serious timing problems , namely wire(More)
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