Masanao Yamaoka

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A multi-stage replica bitline technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40-nm process node, this technique achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%.
Deep-sub-100-nm CMOS LSIs using a bulk CMOS device and a planar double-gate FD-SOI device are compared in terms of the low-voltage limitation of RAM cells, sense amplifiers, and logic gates. The limitation strongly depends on the ever-larger VT variation, especially in SRAM cells and logic gates, and is improved by the FD-SOI. Consequently, two possible(More)
A new computing architecture based on a ground-state search of the Ising model and the probabilistic behavior of a memory cell is proposed. To improve computer performance, a spatial computing architecture that defines an Ising model as the interface between software and hardware is proposed. Various problems can be represented as a spatial parameter in the(More)
Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that(More)
In the near future, the techniques to solve combinatorial optimization problems will become important in various fields and require large computing power. However, the performance growth of von Neumann architecture will slow down due to the end of semiconductor scaling. To resolve this problem, a computing architecture is proposed that maps the optimization(More)