Masana Murase

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The plane sweep algorithm, although widely used in computational geometry, does not parallelize efficiently, rendering it incapable of benefiting from recent trends of multi-core CPUs and general-purpose GPUs. Instead of the plane sweep, some researchers have proposed the uniform grid as a foundation for parallel algorithms of computational geometry, but(More)
This paper proposes “Zero-stop Authentication” system, which requires no intentional interactions between users and authentication applications. Our Zero-stop Authentication model simplifies the current complicated authentication process by automating detection of users and objects. Our challenge is to eliminate the necessity for users to wait for a moment(More)
Current content protection technologies such as those based on broadcast encryption and public-key encryption focus on the distribution and control of content. Although these technologies are effective and mathematically sound, they are susceptible to systematic attacks that utilize any underlying platform weakness, bypassing the cryptographic strengths of(More)
This paper presents the design and implementation of the Cell Broadband Engine <sup>TM</sup>(Cell/B.E.) isolation loader which is a part of the IBM Software Development Kit for Multicore Acceleration [14]. Our isolation loader is a key component in realizing secure application boot and encrypted application execution. During the application load process,(More)
This paper proposes “Zero-stop Authentication” model and system, which realizes automatic, real-time authentication in the physical world. Applications in the physical environment such as those at library gates and supermarket counters could benefit from automatic authentication of users. These applications need to detect users using embedded sensors, and(More)
Overlapping computations and communication is a key to accelerating stencil applications on parallel computers, especially for GPU clusters. However, such programming is a time-consuming part of the stencil application development. To address this problem, we developed an automatic code generation tool to produce a parallel stencil application with latency(More)
This paper presents a novel parallel programming framework that orchestrates multiple languages such as C, C++, and Fortran and multiple computational architectures such as x86, POWER, and NVIDIA's Fermi to enhance productivity of parallel stencil applications while supporting high performance. Unlike traditional parallel programming frameworks, our(More)
Overview of presentation This presentation shows an overview of the “Smart Space 2” project in Keio University [1,2] which aims to realize improvised ubiquitous smart computing environment1. We developed Smart Space Lab (SSLab) [3] which is the room with embedded computation. The SSLab contains numerous types of networked appliances, sensors, and computers(More)