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We propose a novel replacement algorithm, called Inter-Reference Gap Distribution Replacement (IGDR), for set-associative secondary caches of processors. IGDR attaches a weight to each memory-block, and on a replacement request it selects the memory-block with the smallest weight for eviction. The time difference between successive references of a(More)
DCFA-MPI is an MPI library implementation for Intel Xeon Phi co-processor clusters, where a compute node consists of an Intel Xeon Phi co-processor card connected to the host via PCI Express with InfiniBand. DCFA-MPI enables direct data transfer between Intel Xeon Phi co-processors without assistance from the host. Since DCFA, a direct communication(More)
tRNA 3' processing endoribonuclease (3' tRNase) is an enzyme responsible for the removal of a 3' trailer from precursor tRNA (pre-tRNA). We purified approximately 85 kDa 3' tRNase from pig liver and determined its partial sequences. BLAST search of them suggested that the enzyme was the product of a candidate human prostate cancer susceptibility gene,(More)
Two sets of experiments were conducted to examine the effects of two sensory modalities, temperature and taste, of foods on perceptual and motor aspects of swallowing in 20 young, healthy subjects (10 subjects for each experiment). A tasteless and odorless thickening agent was the basic testing material. The first experiment compared the swallowing of foods(More)
We propose a speculative multi-threading processor architecture called Pinot. Pinot exploits parallelism over a wide range of granularities without modifying program sources. Since exploitation of fine-grain parallelism suffers from limits of parallelism and overhead incurred by parallelization, it is better to extract coarse-grain parallelism. Coarse-grain(More)
Many-core architectures, such as the Intel Xeon Phi, provide dozens of cores and hundreds of hardware threads. To utilize such architectures, application programmers are increasingly looking at hybrid programming models, where multiple threads interact with the MPI library (frequently called "MPI+X" models). A common mode of operation for such applications(More)
In this paper we present "Casper," a process-based asynchronous progress solution for MPI one-sided communication on multi- and many-core architectures. Casper uses transparent MPI call redirection through PMPI and MPI-3 shared-memory windows to map memory from multiple user processes into the address space of one or more ghost processes, thus allowing for(More)
SQL-based languages are widely used for Software-based Complex Event Processing (CEP) systems. This paper proposes a FPGA acceleration framework to compile a SQL-based event processing language, which is based on the ANSI standard proposal to support event processing, into a high-performance CEP engine on FPGAs. Besides the SQL's primitives such as(More)
In Sphingomonas paucimobilis UT26, LinD and LinE activities, which are responsible for the degradation of gamma-hexachlorocyclohexane, are inducibly expressed in the presence of their substrates, 2,5-dichlorohydroquinone (2,5-DCHQ) and chlorohydroquinone (CHQ). The nucleotide sequence of the 1-kb upstream region of the linE gene was determined, and an open(More)
The increasing prevalence of co-processors such as the Intel Xeon Phi, has been reshaping the high performance computing (HPC) landscape. The Xeon Phi comes with a large number of power efficient CPU cores, but at the same time, it's a highly memory constraint environment leaving the task of memory management entirely up to application developers. To reduce(More)