Masamichi Ishii

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— This paper describes the architecture and principles of operation of sigma-delta (Σ∆) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe a multi-bit Σ∆ TDC architecture for fast testing. However, mismatches among delay cells in delay lines(More)
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