Masahiro Sowa

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This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a first-in-first-out (FIFO) circular queue-registers instead of random access registers. Datum is inserted in the queue-registers in produced order scheme and can be reused. We show that this feature has profound(More)
Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures.(More)
Abstract. In this research work, we present a high-level prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using modular design structure with control logic implemented as a set of communicating state machines, we show hardware emulation and optimizations results of a(More)
Queue based instruction set architecture processor offers an attractive option in the design of embedded systems. In our previous work, we proposed a novel queue processor architecture as a starting point for hardware/software design space exploration for embedded applications. In this paper, we present a high performance 32-bit Synthesizable QueueCore(More)
Queue based instruction set architecture processor offers an attractive option in the design of embedded systems by providing high performance for a specific application. This work describes the design results and methodology of a queue processor core, named QueueCore, as a starting point for applicationspecific processor (ASP) design. By using simple and(More)
The queue computation model offers an attractive alternative for high-performance embedded computing given its characteristics of short instructions and high instruction level parallelism. A queue-based processor uses a FIFO queue to read and write operands through hardware pointers located at the head and tail of the queue. Queue length is the number of(More)
In this paper, we propose a parallel Queue processor architecture (PQP) that uses Queue data structure for operands and results manipulations. The above architecture project, which started a couple of years ago here at Sowa laboratory, features simple pipeline, compact Queue based instruction set architecture, and is targeted for Internet applications and(More)