Martti Valtonen

Learn More
This paper presents a robust partitioning-based model-order reduction (MOR) method, PartMOR, suitable for reduction of very large RLC circuits or RLC-circuit parts of a non-RLC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements, while still preserving good accuracy for the(More)
Parasitic elements play a major role in advanced circuit design and pose considerable run-time and memory problems for the post-layout verification, especially in the case of full-chip extraction. This paper presents a realizable RC(LM)-netlist-in– RC(LM)-netlist-out method to sparsify and reduce the capacitive coupling parasitics in circuits with(More)
This paper proposes a new second-order Model Order Reduction (MOR) method suitable for reducing very large sized RC circuits or RC circuit parts of a non-RC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements. It is shown that the use of the second-order MOR method in(More)
A macro model for a superconducting microstrip line, including dielectric losses and dispersion due to the frequency dependence of the microstrip effective permittivity, is implemented in the circuit simulator and design tool APLAC. A few fundamental principles of superconductivity are first reviewed so as to fathom the significance of some of the(More)
This paper proposes an admittance formulation for improving the stability of the structure-preserving reduced-order interconnect macromodeling algorithm SPRIM and the RLC equivalent circuit synthesis method RLCSYN. A simulation example is presented to show the benefits of admittance formulation.