Martine D. F. Schlag

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— Efficient utilization of Field Programmable Gate Arrays (FPGAs) depends on the ability to determine whether designs will exceed the logic or routing capacities of the devices. Here, we focus on the problem of assessing the routability of designs for FPGAs before place-and-rpute. Specifically, we identify the relevant wmeabilit y t heorles, modify and(More)
In this article we describe our experience and progress in accelerating an FPGA router. Placement and routing is undoubtly the most time-consuming process in automatic chip design or connguring pro-grammable logic devices as reconngurable computing elements. Our goal is to accelerate routing of FPGAs by 10 fold with a combination of workstation clusters and(More)
The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. We report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable(More)
Recent research on FPGA partitioning has focussed on finding minimum cuts between partitions without regard to the routability of the partitioned subcircuits. In this paper we develop a spectral approach to multi-way partitioning in which the primary goal is to produce routable subcircuits while maximizing FPGA device utilization. To assist the partitioner(More)