Martin Zádník

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AtoZ, an automatic traffic organizer, provides control of how network-resources are used by applications. It does this by combining the high-speed packet processing of the NetFPGA with an efficient method for application-behavior labeling. AtoZ can control network resources by prohibiting certain applications and controlling the resources available to(More)
This paper presents an FPGA-friendly approach to tracking elephant flows in network traffic. Our approach, Single Step Segmented Least Recently Used (S<sup>3</sup>-LRU) policy, is a network traffic-friendly replacement policy for maintaining flow states in a Na&#x00EF;ive Hash Table (NHT). We demonstrate that our S<sup>3</sup>-LRU approach preserves(More)
In this paper, an evolutionary approach is used to design multiple constant multipliers (MCMs). As these circuits can be composed of adders, subtractors and shifters, they perform a linear transform. An important consequence is that only a single input value is sufficient to completely evaluate a candidate circuit independently of its size and the bit width(More)
Flow-based network traffic processing, that is, processing packets based on some state information associated to the flows to which the packets belong, is a key enabler for a variety of network services and applications. This form of stateful traffic processing is used in modern switches [1] and routers that contain flow tables to implement forwarding,(More)
—Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources. In(More)
This paper describes the Net COPE platform porting issues to the new generation of the Net FPGA(-10G) cards. Achieved throughput and CPU utilization for various length of packets was measured. It was shown that we are able to reach maximum throughput of 12Gbps without any significant processor load. Xilinx ISE reports approximately 30% of the Net FPGA chip(More)
—Rapidly growing speed and complexity of computer networks impose new requirements on fast lookup structures which are utilized in many networking applications (SDN, fire-walls, NATs, etc.). We propose a novel lookup concept based on the well-known cuckoo hashing, which can achieve good memory utilization, supplemented by a binary search tree for offloading(More)