Martin Trentzsch

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This work shows how fast wafer-level reliability (fWLR) inline tests allow to quickly screen the intrinsic reliability of High-k / Metal Gate (HK/MG) process splits in an effective manner. Various Hf based gate stack compositions such as pure HfO<inf>2</inf>, Hf<inf>x</inf>Zr<inf>1-x</inf>O<inf>2</inf> and Hf<inf>x</inf>Si<inf>1-x</inf>O<inf>2</inf> are(More)
In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the selective control of nMOS and pMOS GOX, pMOS degradation in(More)
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