Martin Saint-Laurent

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This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium® 4 microprocessor. These values imply(More)
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the microarchitectural impact of using multiple PLLs for clock distribution. Two PLL phase(More)
This paper discusses a novel clock gating cell (CGC) optimized for low-power and low-voltage operation. First, the limitations of the conventional CGC topology are analyzed and several improvements are proposed. Next, the new CGC topology is introduced and compared to the conventional one in terms of dynamic clock power, leakage, area, timing, and(More)
An 18 year-old male first presented a clinical picture of acute psychosis with two recurrences at ages 22 and 23. The diagnosis made at that time was paranoid schizophrenia. Twelve years after his first psychiatric hospitalization, it was discovered that he was suffering from Wilson's disease. In retrospect, the clinical picture was atypical, notably with(More)
This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-longinstruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low(More)
A novel circuit approach to increase SRAM Static Noise Margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like Negative Bias Temperature Instability (NBTI) [3] all contribute to raising the minimum voltage required for stable SRAM. Our strategy(More)
A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six(More)
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little(More)
This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual(More)