Martin Kaibel

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This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed(More)
Standard automated test equipment (ATE) for radio frequency (RF) transceiver production testing of today is limited by digital signal processing and data transfer. These constraints can be considerably relaxed by the application of new technology based on field programmable gate array (FPGA). The methods proposed are capable of handling all tasks flexibly(More)
This paper describes the hierarchical test-generation method STAR-DUST, using selftest program generator RESTART, test pattern generator DUST, fault simulator FAUST and SYNOPSYS logic synthesis tools. RESTART aims at supporting self-test of embedded processors. Its integration into the STAR-DUST environment allows test program generation for realistic fault(More)
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