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Carry-save arithmetic based architectures are becoming popular in VLSI designs. However, few designs are available for 2's complement carry-save multipliers. The carry-save outputs from conventional… (More)
Process integration of two manufacturable high performance 0.5-/spl mu/m CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The… (More)
We present predictive and accurate modeling of base and collector currents in poly‐Si emitter bipolar transistors Ref. . Using a standard 0.8 μm bipolar complementary metal–oxide–semiconductor… (More)
Two manufacturable high performance 0.5 pm CMOS technologies, one optimized for 5 V operation and the second optimized for 3.3 V operation, are presented. An improvement of 2 in circuit performance,… (More)