Marlene Wan

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Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural(More)
In this paper, we present and analyze a number of interconnect architectures for reconfigurable systems targeting applications in the areas of wireless communication and multimedia processing. Several interconnect archi-tectures suitable for heterogeneous elements are proposed and then a methodology to evaluate the architectures is described. The results(More)
—A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm 6.7 mm prototype processor , targeted for voice compression, is implemented in a 0.25-m 6-metal CMOS process, and consumes 1.8 mW at an(More)
Heterogeneous reconfiguration enables the flexible implementation of baseband wireless functions at energy levels between 50 and 100 MIPS/mW, 8 times lower than traditional DSP processors. A 5.2×6.7 mm 2 prototype processor, targeted for voice compression is implemented in a 0.25 µm 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of(More)
The advent of the third generation of wireless applications creates a need for processing modules that simultaneously display high computational performance, ultra low-energy consumption and a high degree of flexibility and adaptability. The flexibility and adaptability is a necessity in the presence of multiple and evolving standards, and increases(More)
The continually increasing integration density of integrated circuits portrays important paradigm shifts in next-generation designs, especially in the direction of systems-on-a-chip. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. This opens the door for creative high-performance low-energy solutions(More)
In this paper we describe a code generation and optimization process for reconfigurable architectures targeting digital signal processing and wireless communication applications. The ability to generate efficient and compact code is essential for the success of reconfigurable architectures. Otherwise, the overhead of reconfiguring could easily become the(More)
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a variety of the macromodules (micro-processors, DSPs, programmable logic and embedded memories) are being reported by a number of companies. Most of these systems target the embedded market where(More)