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A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm 6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25m 6-metal CMOS process, and consumes 1.8 mW at an(More)
In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband(More)
Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural(More)
In this paper, we present and analyze a number of interconnect architectures for reconfigurable systems targeting applications in the areas of wireless communication and multimedia processing. Several interconnect architectures suitable for heterogeneous elements are proposed and then a methodology to evaluate the architectures is described. The results(More)
Heterogeneous reconfiguration enables the flexible implementation of baseband wireless functions at energy levels between 50 and 100 MIPS/mW, 8 times lower than traditional DSP processors. A 5.2×6.7 mm prototype processor, targeted for voice compression is implemented in a 0.25 μm 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40(More)
The continually increasing integration density of integrated circuits portrays important paradigm shifts in next-generation designs, especially in the direction of systems-on-a-chip. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. This opens the door for creative highperformance low-energy solutions(More)
The advent of the third generation of wireless applications creates a need for processing modules that simultaneously display high computational performance, ultra low-energy consumption and a high degree of flexibility and adaptability. The flexibility and adaptability is a necessity in the presence of multiple and evolving standards, and increases(More)
Reconfigurable architectures have emerged as a promising implementation platform to provide high-flexibility, high-performance, and lowpower solutions for future wireless embedded devices. We discuss in details a reconfigurable data-flow driven architecture, including the computation model, communication mechanism, and implementation. We also describe a set(More)
In this paper we describe a code generation and optimization process for reconfigurable architectures targeting digital signal processing and wireless communication applications. The ability to generate efficient and compact code is essential for the success of reconfigurable architectures. Otherwise, the overhead of reconfiguring could easily become the(More)