Markus Wimplinger

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  • Rama Puligadda, Sunil Pillalamarri, Wenbin Hong, Chad Brubaker, Markus Wimplinger, Stefan Pargfrieder
  • 2007
Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking,(More)
Packaging costs of Micro-Electro-Mechanical System (MEMS) are still contributing with >50% to the total costs of most devices. Aligned wafer bonding techniques for Wafer-level packaging (WLP) demonstrates a huge potential to reduce these costs due to a smaller size of the total package, improved performance and shorter time to market. A special group of(More)
The purpose of this extended abstract is to present a new application of spray coating process which greatly improves the process of performing underfill of suspended structures (air bridges) with low-k polymer. By using spray coating, it is possible to realize as much as a nine-fold materials savings, plus a three fold time savings. This article describes(More)
The continuation of Moore’s law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requireing huge capital investments. On proposed scenario is the implementation of compound semiconductors as parts of advanced CMOS devices for More-than-Moore integration. The continuation of improved performance(More)
Packaging costs of Micro-Electro-Mechanical System (MEMS) are still contributing with >50% to the total costs of most devices. Aligned wafer bonding techniques for Wafer-level packaging (WLP) demonstrates a huge potential to reduce these costs due to a smaller size of the total package, improved performance and shorter time to market. A special group of(More)
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