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Damage in the older needles of Norway spruce [Picea abies (L.) Karst.] in the Fichtelgebirge (NE Bavaria, FRG) appears to result primarily from nutrient imbalances rather than from direct effects ofâ€¦ (More)

- Evgeny Pavlenko, Markus Wedler, +4 authors Gert-Martin Greuel
- 2011 Design, Automation & Test in Europe
- 2011

This paper presents a new SMT solver, STABLE, for formulas of the quantifier-free logic over fixed-sized bit vectors (QF-BV). The heart of STABLE is a computer-algebra-based engine which providesâ€¦ (More)

- Minh D. Nguyen, Max Thalmaier, Markus Wedler, JÃ¶rg Bormann, Dominik Stoffel, Wolfgang Kunz
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 2008

We propose a methodology to formally prove protocol compliance for communication blocks in System-on-Chip (SoC) designs. In this methodology, a set of operational properties is specified with respectâ€¦ (More)

This paper proposes a new approach for proving arithmetic correctness of data paths in System-on-Chip modules. It complements existing techniques which are, for reasons of complexity, restricted toâ€¦ (More)

- Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 2007

We propose a normalization technique for verifying arithmetic circuits in a bounded model-checking environment. Our technique operates on the arithmetic bit-level (ABL) description of the arithmeticâ€¦ (More)

- Markus Wedler, Dominik Stoffel, Wolfgang Kunz
- Proceedings Design, Automation and Test in Europeâ€¦
- 2004

We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level description of theâ€¦ (More)

- Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi, Matthias Pflanz
- 2008 Asia and South Pacific Design Automationâ€¦
- 2008

In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We define a multiplier description language which abstracts from low-level optimizationsâ€¦ (More)

- Markus Wedler, Dominik Stoffel, Wolfgang Kunz
- Proceedings. 42nd Design Automation Conferenceâ€¦
- 2005

We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the <i>arithmetic bit level (ABL) description</i> of theâ€¦ (More)

- Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 2004

This paper discusses a "structural" technique for traversing the state space of a finite state machine (FSM) and its application to equivalence checking of sequential circuits. The key ingredient toâ€¦ (More)