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In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing. There are two main aspects to the application of formal methods in a design process: the formal framework used to specify(More)
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a simple test xture, it operates at data rates of 120 Mbits/sec over a pair of wires. Because STARI uses both synchronous and self-timed circuits, it provides an opportunity to(More)
Recently, researchers at Rambus proposed a ring-oscillator example as a challenge problem for analog verification: they asked researchers to identify conditions that will ensure that the oscillator is free from lock-up. We present a solution to this challenge problem. Our approach is primarily pencil-and-paper analysis. We prove properties of the oscillator(More)
With increasing integration densities, large chip designs are commonly partitioned into multiple clock domains. While the computation within each individual domain may be synchronous, the interfaces between these domains often use asynchronous methods. One such approach is the STARI technique[12, 13] where a self-timed FIFO compensates for clock-skew(More)
Pre-designed and pre-verified hardware and software blocks can be combined on chips for many different applicationsVthey promise large productivity gains. ABSTRACT | Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred(More)
We show that the problem of finding an energy minimal schedule for execution of a collection of jobs on a multiprocessor with job migration allowed has polynomial complexity. Each job is specified by a release time, a deadline, and an amount of work to be performed. All of the processors have the same, convex power-speed trade-off of the form P = phi(s),(More)
&SINGLE-CLOCKED DIGITAL SYSTEMS are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous,(More)