Learn More
—We investigate a new class of codes for the optimal covering of vertices in an undirected graph G such that any vertex in G can be uniquely identified by examining the vertices that cover it. We define a ball of radius t centered on a vertex v to be the set of vertices in G that are at distance at most t from v: The vertex v is then said to cover itself(More)
All known results on covering radius are presented, as well as some new results. There are a number of upper and lower bounds, including asymptotic results, a few exact determinations of covering radius, some extensive relations with other aspects of coding theory through the Reed-Muller codes, and new results on the least covering radius of any linear [II,(More)
Network calculus is known to apply in general only to feedforward routing networks, i.e., networks where routes do not create cycles of interdependent packet flows. In this paper, we address the problem of using network calculus in networks of arbitrary topology. For this purpose, we introduce a novel graph-theoretic algorithm, called turn-prohibition (TP),(More)
— We will say that code C detects error e with probability 1 − Q(e), if Q(e) is a fraction of codewords y such that y, y + e ∈ C. We present a class of optimal nonlinear q-ary systematic (n, k)-codes (robust codes) minimizing over all (n, k)-codes maxima of Q(e) over all e = 0. We will also show that any linear (n, k))-code Vwith n ≤ 2k can be modified into(More)
The early propagation effect found in many logic gates is a potential source of data-dependent power consumption. We show that the effect and the corresponding power dependency can be targeted for successful power analysis attacks in cryptographic hardware. Many of the current balanced gate designs did not directly consider the effect and are vulnerable to(More)
Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reliability methods are used primarily only to ensure the correctness of the logical functionality and not the balance of a circuit. Due to the hardware redundancy in balanced gate designs,(More)
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area overhead and the number of crosspoint devices are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault(More)