Mark Carruthers

Learn More
Through-Silicon Vias [TSV] offer improved system performance by reducing interconnect length to increase device speeds, and by using stacking to reduce package form-factors and enabling heterogeneous device integration. Via Reveal' [VR] - a sequence of wafer back side process steps - is key to the successful implementation of TSV. After via formation,(More)
This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >;5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ~200:1 can be achieved on bonded TSV wafers. A novel end-point detection method will also be presented allowing control of the(More)
In this paper, we describe the importance of carefully selecting the wafer backside processes in 3D stacked IC process flows. In particular, we report on the impact of TSV Via-middle reveal and backside passivation processes on the C-V characteristic of the TSV. The cause of anomalous C-V inversion of the TSV capacitor is explained and a solution is given(More)
This paper reports on the development of low temperature (<;190°C) plasma-enhanced chemical vapour deposition (PECVD) processes used to deposit silicon oxide/silicon nitride film stacks for use as passivation layers over exposed through-silicon vias in thinned (<;60μm), 300mm silicon wafers, temporarily bonded to silicon or glass(More)
This paper discusses the optimisation of plasma etch and deposition processes used in interposer and “via middle” schemes to reveal and passivate through-silicon vias [TSV] on the back sides of 300mm silicon wafers, thereby enabling subsequent contact, bonding and stacking processes. A dual source inductively-coupled etch system with innovative in-situ(More)
  • 1