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designed at multiple levels of abstraction, including the layout, transistor, gate, registertransfer (RTL), and architecture (behavioral) levels. Designers describe circuits in a hierarchical, top-down fashion, typically using computer-aided design (CAD) tools. To simplify the design process, designers try to model circuits at a fairly abstract level, such(More)
A high-level fault modeling and testing philosophy is proposed which is aimed at ensuring,full detection of low-level, physical faults, as well as the industry-standard single stuck-line (SSL) faults. A set of independent functional faults and the corresponding ,functional tests are derived (induced) from the circuit under test; ofparticulur interest are(More)
Reprints available directly from the publisher Photocopying permitted by license only (C) 2001 OPA (Overseas Publishers Association) N.V. We present novel test set encoding and pattern decompression methods for core-based systems. These are based on the use of twisted-ring counters and offer a number of important advantages-significant test compression(More)
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