Mark Bolliger

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The implementation of a first-generation CELL processor that supports multiple operating systems including Linux consists of a 64 bit power processor element (PPE) and its L2 cache, multiple synergistic processor elements (SPE) (B. Flachs et al.) each with its own local memory (LS) (T. Asano et al.), a high bandwidth internal element interconnect bus (EIB),(More)
This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above(More)
This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to(More)
The implementation of a first-generation CELL processor that supports multiple operating systems including Linux consists of a 64b power processor element (PPE) and its L2 cache, multiple synergistic processor elements (SPE) [1] that each has its own local memory (LS) [2], a high-bandwidth internal element interconnect bus (EIB), two configurable(More)
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