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The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2x when compared to the recent state-of-the-art decoder architectures.
The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data-reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction… (More)
—Belief propagation (BP) is a powerful algorithm to decode low-density parity check (LDPC) codes over additive white Gaussian noise (AWGN) channels. However, the traditional BP algorithm cannot adapt efficiently to the statistical change of SNR in an AWGN channel. This paper proposes an adaptive scheme that incorporates a particle filtering (PF) algorithm… (More)
Message passing memory takes around 30% of chip area and consumes from 50%-90% power of the typical semi-parallel decoders for the Low Density Parity Check Codes (LDPC). We propose a new LDPC Decoder architecture based on the Min Sum algorithm that reduces the need of message passing memory by 80% and the routing requirements by more than 50%. This novel… (More)
The focus of this paper is to provide a framework for the joint optimization of both the coefficient quantization and multiple constant multiplication (MCM) problems. It is known that while the MCM problem is complete in the subspace of integer constants, it is incomplete and not optimal in the real world where the MCM constants are often noninteger. In… (More)
This paper discusses a real-time digital signal processor (DSP)-based hierarchical neural network classifier capable of classifying both analog and digital modulation signals. A high-performance DSP processor, namely the TMS320C6701, is utilized to implement different kinds of classifiers including a hierarchical neural network classifier. A total of 31… (More)