• Publications
  • Influence
Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols
Last level caches (LLC) play an important role in current and future chip multiprocessors, since they constitute the last opportunity to avoid expensive off-chip accesses. In a tiled CMP, the LLC isExpand
  • 12
  • 2
  • Open Access
Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support
Chip Multiprocessor Systems (CMPs) rely on a cache coherency protocol to maintain memory access coherence between cached data and main memory. The Hammer coherency protocol is appealing as itExpand
  • 27
  • 1
  • Open Access
Heterogeneous network design for effective support of invalidation-based coherency protocols
Future chip multiprocessors will include tens and hundreds of cores organized in a tile-based design pattern. A built-in on-chip network (NoC) will be devoted to communicating processors and memoryExpand
  • 9
Built-in fast gather control network for efficient support of coherence protocols
Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocolExpand
  • 5
An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance
  • M. Lodde, J. Flich
  • Computer Science
  • Seventh IEEE/ACM International Symposium on…
  • 21 April 2013
In future many-core chip systems, virtualization of chip resources will become mandatory in order to get the maximum chip utilization and provide the maximum possible service to demandingExpand
  • 2
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems
Display Omitted A high-throughput low-latency network for snoop-based cache coherence protocol is proposed.Execution time and power consumption are reduced meanwhile area over-head is keptExpand
  • 1
Runtime home mapping for effective memory resource usage
Abstract In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poorExpand
  • 1
Area-Efficient Snoopy NoC Design for High-Performance Chip Multiprocessor Systems
Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improvesExpand
A Lightweight Network of IDs to Quickly Deliver Simple Control Messages
Most of the network traffic in a Chip Multiprocessor (CMP) is due to messages exchanged by the caches according to the cache coherence protocol. Different types of messages have differentExpand
MP-07.04