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A 14nm logic technology using 2 nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal(More)
A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3 rd-generation high-k + metal-gate technology and a 5 th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides(More)
The ISTIMES project, funded by the European Commission in the frame of a joint Call "ICT and Security" of the Seventh Framework Programme, is presented and preliminary research results are discussed. The main objective of the ISTIMES project is to design, assess and promote an Information and Communication Technologies (ICT)-based system, exploiting(More)
– Intel Corporation is delivering myriad presentations, panel discussions and demonstrations at this year's VLSI Symposia. A highlight paper discloses new details about Intel's 22nm process – the industry's first fully depleted 3-D tri-Gate technology with superior low voltage and low power capabilities. Other Intel papers describe innovations in reducing(More)
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