Mariano Aguirre

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This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35μm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840μW, respectively.(More)
CONSISTENCY IN MICROCALCIFICATION DETECTION Olga Kosheleva, Jesus Arenas, Mariano Aguirre, Carlos Mendoza, and Sergio D. Cabrera Dept. of Electrical and Computer Engineering University of Texas at El Paso El Paso Texas 79968-0523 U.S.A. folga,cabrerag@ece.utep.edu ABSTRACT In this paper we motivate, de ne and illustrate the behavior of four scalar metrics(More)
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