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This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35μm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840μW, respectively.(More)
In this paper we motivate, deene and illustrate the behavior of four scalar metrics which measure the degree to which microcalciication (Ca++) detection is aaected by lossy compression distortion. The JPEG method is used at various compression rates determined by a single parameter. Our metrics are specifically targeted to measure the degree of invariance(More)
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