Marek Tudruj

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New architectural solutions for parallel systems built of bus-based shared memory processor clusters are presented. A new paradigm is proposed for interprocessor communication, called communication on the fly. With this paradigm, processors can be dynamically switched between clusters at program run-time to bring in their caches data that can be read by(More)
The paper presents a new architecture for systems based on run-time reconfigured shared memory processor clusters meant for implementation using network on chip technology. Clusters constitute local data exchange sub-networks, which dynamically connect processors with shared memory modules. The sub-networks enable exposure of data from one processor's data(More)
We concern parallel computations with communication based on remote direct memory access (RDMA), which provides low level un-buffered access to distributed memory of computational nodes. Fine grain computations involve very frequent transmissions of small messages. For their efficient execution with RDMA communication a special memory infrastructure -(More)
Many computational problems have irregular data/control characteristics, which make programs difficult to be efficiently implemented in parallel systems. Due to irregular character of code or data, even division of work between processors at application startup is frequently impossible. Runtime optimization is possible, but it requires a constant exchange(More)
A new distributed program graphical design environment is described in the paper. It is oriented towards designing program execution control based on a built-in system infrastructure which enables easy global application states monitoring in systems based on multicore processors. Two aspects of global application control design are covered. First is the(More)
The paper presents an analysis of the suitability of the architecture of dynamic SMP clusters with communication on the fly for massively parallel fine grain numerical computations. It is assumed that the proposed architecture is implemented using the highly modular "system on chip" and "network on chip" technology. This technology is considered to provide(More)