Marek Syrzycki

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The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES IC's. Selected state-of-the-art devices: 10 Gb/s line side SERDES and backplane drivers are discussed in detail. Particular emphasis is placed on challenges associated with design of(More)
This paper presents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13 μm CMOS technology. The simulation results demonstrate(More)