Marek Syrzycki

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— A mixed-signal continuous time behavioral model of a continuous time delta-sigma modulator (CT ∆Σ) is presented. CT ∆Σ modulators, by their nature, are mixed-signal systems. That fact creates a discontinuity in the traditional IC design flow which assumes that " discrete " and " continuous " time domain designs require separate design tools. In this work,(More)
The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES ICs. Selected state-of-the-art devices: 10 Gb/s line side SERDES and backplane drivers are discussed in detail. Particular emphasis is placed on challenges associated with design of(More)
The goal of this paper is to investigate design parameters of the CMOS STI diodes, intended to be used as ESD protection devices, and evaluate their performance for use in the deep submicron CMOS process. The 2-D simulations of multiple diode structures and geometries have been performed using SEQUOIA Device Designer, and the results allow to accurately(More)
This paper presents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13 μm CMOS technology. The simulation results demonstrate(More)
In this paper, we discuss the noise contribution of the current source transistors in the charge sensitive amplifier for application in the front-end semiconductor radiation detectors. We developed an analytical methodology that allow to determine the optimum geometry for the current source transistors, so that the current source transistor ends up(More)