Marek Syrzycki

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An analytical design methodology for continuoustime (CT) bandpass (BP) modulators is presented. Secondand fourth-order tunable continuous time BP modulator design equations are presented. A novel loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the(More)
The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES ICs. Selected state-of-the-art devices: 10 Gb/s line side SERDES and backplane drivers are discussed in detail. Particular emphasis is placed on challenges associated with design of(More)
A mixed-signal continuous time behavioral model of a continuous time delta-sigma modulator (CT ∆Σ) is presented. CT ∆Σ modulators, by their nature, are mixed-signal systems. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. In this work, we(More)
Multiple designs of silicon controlled rectifier (SCR) devices as major electrostatic discharge (ESD) protection circuits in 0.35 micron CMOS technology are investigated to provide better insight into their operation. They are also compared with the conventional CMOS ESD protection circuits to investigate possible advantages in smaller silicon area,(More)
This paper investigates substrate noise propagation and attenuation with a focus on analysis for deep submicron structures and short propagation distances. The discussed issues include effects of noise source/target doping types, noise source and target separation distances, presence of guard rings, and the utilization of deep-well structures on noise(More)
Reports on the optimization of a latched comparator for use in a high speed analog to digital converter (ADC). Optimization of the comparator was achieved through variations of transistor dimensions and layout designs. Specifically three layout styles, fill-analog style, partial-analog style and digital-like style were created in 0.5 /spl mu/m MOSIS and(More)
2.5 GHz phase-locked loop (PLL) suitable for system-on-the-chip (SOC) implementation is presented. PLL can be configured as a clock multiplication unit (CMU) or as a clock recovery unit (CRU) for data muxing or jitter clean-up applications. It uses a phase-frequency detector (PFD), a low voltage charge-pump, and a low power H-bridge output driver. Phase(More)