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For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. We have designed and optimized four high performance parallel GF (2) multipliers for an FPGA realization and analyzed the time and area complexities. One of the multipliers uses a new hybrid structure to implement… (More)

For FPGA based coprocessors for elliptic curve cryptography, a significant performance gain can be achieved when hybrid coordinates are used to represent points on the elliptic curve. We provide a new area/performance tradeoff analysis of different hybrid representations over fields of characteristic two. Moreover, we present a new generic cryptoprocessor… (More)

- Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
- 18th International Parallel and Distributed…
- 2004

Summary form only given. By increasing the amount of resources on reconfigurable platforms with the ability of partial reconfigurability, the issues of the management of these resources and their sharing among different tasks will become more of a concern. Online placement is one of these management issues that are investigated. We present a new approach… (More)

- Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka
- ASAP
- 2000

Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the low performance, while realizing multiprocessor sorting methods on parallel computers is much too expensive with respect to power consumption, physical weight, and cost. We… (More)

FPGA based VLSI processor arrays provide an enormous computation performance along with the flexibility of reconfigurable logic. In the future, hybrid processors will become available that consist of a RISC core and configurable logic area on the same die. This allows for the efficient usage of a VLSI array as a coprocessor to the RISC core. Due to their… (More)

- Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
- IPDPS
- 2004

- Marcus Bednara, Jürgen Teich
- The Journal of Supercomputing
- 2003

We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there… (More)

- Marcus Bednara, Frank Hannig, Jürgen Teich
- Embedded Processor Design Challenges
- 2002

We present a new methodology for controlling the space-time behavior of VLSI and FPGA-based processor arrays. The main idea is to generate simple local control elements which take control over the activeness of each attached processor element. Each control element thereby propagates a “start” and a “stop execution” signal to its neighbors. We show that our… (More)

FPGAs are an attractive platform for elliptic curve cryptography hardware. Since field multiplication is the most critical operation in elliptic curve cryptography, we have studied how efficient several field multipliers can be mapped to lookup table based FPGAs. Furthermore we have compared different curve coordinate representations with respect to the… (More)

We consider the problem of automatically mapping computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there… (More)