Marco Erstling

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In this paper we present a tool based approach for an aging-aware design method. Extending the g<sup>m</sup>/I<sup>D</sup> sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design(More)
In this paper a tool based on the g<inf>m</inf>/I<inf>D</inf>-methodology is presented to provide information on operating point-dependent degradation in integrated circuits caused by NBTI and HCI during early design stages. The advantage of the presented GMID-Tool is that it does not require any further SPICE or aging simulations after the extraction of(More)
For mixed signal applications it is necessary to have metallization which are able to carry high currents. Also the on chip integration leads to special requirements on the metallization concerning their robustness. A common method for the determination of interconnect lifetime is described in JP001A and based on Black's law and the measurement of time to(More)
The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metallization in semiconductor back end of line (BEOL) structures. The elements of the metal stack have different(More)
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