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Transaction Level Modeling (TLM) is gaining more and more importance to quickly evaluate design alternatives in multimedia systems and other mixed HW/SW systems. However, the comprehensive and automated verification of TLM models is still a difficult challenge. In previous work, we presented an approach for model checking of SystemC/TLM designs based on a(More)
—SystemC is widely used for modeling and simulation in hardware/software co-design. However, the co-verification techniques used for SystemC designs are mostly ad-hoc and non-systematic. A particularly severe drawback is that simulation results have to be evaluated manually. In previous work, we proposed to overcome this problem by conformance testing. We(More)
Memory safety plays a crucial role in concurrent hardware/-software systems and must be guaranteed under all circumstances. Although there exist some approaches for complete verification that can cope with both hardware and software and their interplay, none of them supports pointers or memory. To overcome this problem, we present a novel approach for model(More)
SystemC is a system level design language that is widely used in hardware/software codesign. As the semantics of SystemC is only informally defined, verification of SystemC designs is mainly done using simulation and testing. With that, faults can be detected but it is impossible to verify the correctness of a given system for all possible executions. In(More)
Concurrent designs can be automatically verified by transforming them into an automata-based representation and by model checking the resulting model. However, when transforming a concurrent design into an automata-based representation , each method has to be translated into a single automaton. This produces a significant overhead for model checking. In(More)
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