Marc Boris Dombrowa

Learn More
advanced diagnostics environment M. E. Giampapa R. Bellofatto M. A. Blumrich D. Chen M. B. Dombrowa A. Gara R. A. Haring P. Heidelberger D. Hoenicke G. V. Kopcsay B. J. Nathanson B. D. Steinmacher-Burow M. Ohmacht V. Salapura P. Vranas This paper describes the Blue Genet/L advanced diagnostics environment (ADE) used throughout all aspects of the Blue Gene/L(More)
compute chip: Synthesis, timing, and physical design A. A. Bright R. A. Haring M. B. Dombrowa M. Ohmacht D. Hoenicke S. Singh J. A. Marcella R. F. Lembach S. M. Douskey M. R. Ellavsky C. G. Zoellin A. Gara As one of the most highly integrated system-on-a-chip application-specific integrated circuits (ASICs) to date, the Blue Genet/L compute chip presented(More)
Soft Error Resiliency (SER) is a major concern for Petascale high performance computing (HPC) systems. In designing Blue Gene/Q (BG/Q) [8], many mechanisms were deployed to target SER including extensive use of Silicon-On-Insulator (SOI), radiation-hardened latches [7,13], detection and correction in on-chip arrays, and very low radiation packaging(More)
compute chip: Control, test, and bring-up infrastructure R. A. Haring R. Bellofatto A. A. Bright P. G. Crumley M. B. Dombrowa S. M. Douskey M. R. Ellavsky B. Gopalsamy D. Hoenicke T. A. Liebsch J. A. Marcella M. Ohmacht The Blue Genet/L compute (BLC) and Blue Gene/L link (BLL) chips have extensive facilities for control, bring-up, self-test, debug, and(More)
ed description of the protocol to prove the correctness of the protocol. The Murphi tool basically enumerates all possible states of the abstracted protocol description. The Murphi tool can easily check for the reachability of harmful states (assertions) or for the possibility to exit any loop in the state transition matrix (livelock or deadlock). Because(More)
Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of(More)
  • 1