María Engracia Gómez

Learn More
— In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of faults without significantly degrading performance. The methodology is mainly based on the(More)
GAP GAP Parallel Architectures Group Grupo de Arquitecturas Paralelas 2 Objective • To propose a deterministic routing algorithm for fat-trees with a similar performance to the adaptive routing algorithm commonly-used in fat-trees – Implicit in-order delivery – More simple hardware implementation • To provide a memory-efficient implementation for the(More)
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as those based on directory caches. However, the limited directory cache size of the increasingly larger systems may cause frequent evictions of directory entries and, consequently,(More)
Most of past evaluations of fat-trees for on-chip interconnection networks rely on oversimplifying or even irrealistic architecture and traffic pattern assumptions, and very few layout analyses are available to relieve practical feasibility concerns in nanoscale technologies. This work aims at providing an in-depth assessment of physical synthesis(More)