Mao-Chih Hsia

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This paper describes an area-efficient variation-tolerant data-aware dynamic supply Write-assist scheme for a cross-point 8T SRAM. A 128Kb test chip implemented in 55nm Standard Performance CMOS technology achieves error free full functionality without redundancy from 1.5V down to 0.5V, with area overhead of only 0.834% for the Data-Aware Write-Assist(More)
This paper describes a high-performance low VMIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bitinterleaving architecture and achieving low VMIN. A 512Kb test chip is(More)
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