Manuel Jesús Bellido Díaz

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In this work, we present a computational behavioralmodel for logic gates called Internode (Internal Node LogicComputational Model) that considers the functionality ofthe gate as well as all the different internal states the gatecan reach. This computational model can be used in logic-leveltools and is valid for any dynamic behavioral model(delay models,(More)
In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal(More)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical(More)