—A high slew-rate amplifier with push–pull output driving capability is proposed to enable an ultra-low quiescent current (1 A) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push–pull output… (More)
Acknowledgment: The development of BSIM3v3.2 benefited from the input of many BSIM3 users, especially the Compact Model Council (CMC) member companies. TSMC for their valuable assistance in identifying the desirable modifications and testing of the new model. their guidance and support.
—The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-m CMOS… (More)
A system-on-chip passive UHF RFID tag with embedded temperature sensor is developed in a standard 0.18µm CMOS process for the EPC Gen-2 protocol from 860-960MHz . Flip-chip technology is used to bond the developed tag IC to an antenna to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications… (More)
1 Abstract—The dual-band recording of the local-field potential (LFP, 0.1Hz~200Hz) and the spike potential (SP, 200Hz~10kHz) is important for physiological studies at the cellular level. Recent study shows that the LFP signal plays important roles in modulating many profound cellular mechanisms. Although various bio-signal acquisition circuits have been… (More)
Web Sites: BSIM4 web site with BSIM source code and documents: Acknowledgement: The development of BSIM4.6.1 benefited from the input of many BSIM users, especially the Compact Model Council (CMC) member companies. and Shigetaka Kumashiro at NEC, Richard Taylor at NSC, for their valuable assistance in identifying the desirable modifications and testing of… (More)
—This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic… (More)
Acknowledgement: The development of BSIM4.7 benefited from the input of many BSIM users, especially the Compact Model Council (CMC) member companies. The developers would like to thank for their valuable assistance in identifying the desirable modifications and testing of the new model.
This paper presents a framework to develop a generic and physical Double-Gate MOSFET model. Due to limited available physical data and existence of a large variety of device structures, flexibility to assemble model modules to accommodate different device structures takes a much high precedence compared with conventional modeling approaches. In addition,… (More)