Learn More
A high slew-rate amplifier with push–pull output driving capability is proposed to enable an ultra-low quiescent current ( 1 A) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push–pull output(More)
The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35m CMOS(More)
Figure 17.1.1 shows the block diagram of the tag IC. Multiple supply voltages, generated by a power management unit (PMU) using a separate-storage-capacitor technique to save area, are employed to optimize the performance of individual building blocks, while minimizing the total power consumption. A dualpath clock generator is used to generate on-chip(More)
 Abstract—The dual-band recording of the local-field potential (LFP, 0.1Hz~200Hz) and the spike potential (SP, 200Hz~10kHz) is important for physiological studies at the cellular level. Recent study shows that the LFP signal plays important roles in modulating many profound cellular mechanisms. Although various bio-signal acquisition circuits have been(More)
In order to be useful for mobile systems, the switching frequencies of modern buck converters (BCs) are in the MHzor even GHzrange to enable the use of compact off-chip inductors and capacitors [1], or even on-chip Ls and Cs [2]. However, such high switching frequencies increase both the switching loss and the gate-drive loss, and degrade BC light-load(More)
Microelectrodes are widely used in the physiological recording of cell field potentials. As microelectrode signals are generally in the μV range, characteristics of the cell-electrode interface are important to the recording accuracy. Although the impedance of the microelectrode-solution interface has been well studied and modeled in the past, no effective(More)
This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to(More)
In this paper, a new Correlated Double Sampling (CDS) Technique based on Fixed Voltage Difference (FVD) is introduced. Compared with the traditional CDS technique with voltage sampling for A/D conversion, this method has the advantage of low voltage capability, which relieves the high resolution requirement of the subsequent A/D converter as a result of the(More)
In this paper we report the fully depleted CMOS/SO1 device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design. The differences and similarities are summarized. We believe this is the first such study to be reported.