Manisha Pattanaik

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— The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the(More)
In the age of scaled silicon technology to improve the functional efficiency of a CM OS design, the device geometry and device parameters are constantly scaled. The major factors of the power consumption due to continuous reduction of the oxide thickness (t OX) is the gate leakage current in both the active and standby mode of the device and other is due to(More)
This paper provides a robust scheme for random valued impulsive noise reduction along with edge preservation by anisotropic diffusion with improved diffusivity. The defective impulse noisy pixels are detected by Laplacian based second order pixel difference operation where these defective pixels are replaced by appropriate values with regard of the gray(More)
Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced,(More)
This paper provides the use of rule based fuzzy scheme to define a new diffusion coefficient function in anisotropic diffusion for impulse noise removal with edge preservation. This is achieved by expressing the small, medium and large labels of second order pixel differences in fuzzy format. An aggregated output membership function of percentage of(More)