Manisha Pattanaik

Learn More
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground(More)
In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. Virtex-6 is 40-nm FPGA, on which we implement our circuit to re-assure power reduction in sequential circuit. Clock gating is implemented on smaller circuit called D flip-flop and on(More)
The progressive scaling demands effort from both the circuit and the device level, to cope with circuit variability and reliability issues. Advent of FinFET technology has suppresses the short channel effects and variability, but still suffers with self heating problem consequently increases temporal degradations. In this paper, we investigate severity of(More)
Wide Fan-in dynamic OR gate has always been an integral part of high speed microprocessors. But dynamic logic gate suffers from low noise immunity. A weak PMOS keeper was introduced to increase the noise immunity. Keeper technique acts as a compensatory mechanism for charge loss due to leakage current and maintains high noise immunity while allowing leakage(More)
This paper provides a detailed performance analysis of low power and high speed Look up Table (LUT) by using a circuit technique. Proper sizing of all the sleep transistors are done in the LUT to achieve an optimum power –delay relationship so that it can be used for fast growing low power applications. Also, we have implemented a benchmark circuit(More)