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An on-chip data jitter measurement circuit in 0.11-mum CMOS is demonstrated. It utilizes a data-to-clock converter, pulse generators, and an integrator followed by a sample-&amp;-hold. The circuit outputs a data jitter waveform in real-time, and doesn't require a reference clock. Its measurement linearity is 11 muV/ps with an error of 1.56 ps<sub>RMS</sub>(More)
Static tests are key in reducing the current high cost of testing analog and mixed-signal ICs. A new DC test generation technique for detecting catastrophic failures in this class of circuits is presented. To include the effect of tolerance of parameters during testing, the test generation problem is formulated as a minimax optimization problem, and solved(More)
This paper presents a new zero dead-time architecture for data jitter measurement, which is suitable for on- or off-chip implementations. Two circuits for measurement of data-dependent jitter (DDJ), random jitter (RJ), and sinusoidal jitter (SJ) are demonstrated. The circuits were implemented in a 0.11-mum CMOS process with 1.2-V supply. They utilize a(More)