Mangesh Sadafale

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This paper describes the core transforms specified for the high efficiency video coding (HEVC) standard. Core transform matrices of various sizes from 4 × 4 to 32 × 32 were designed as finite precision approximations to the discrete cosine transform (DCT). Also, special care was taken to allow implementation friendliness, including limited bit(More)
This paper describes the analog and power management aspects of a single chip asymmetric digital subscriber line (ADSL) customer premises equipment (CPE) router. We address the system partitioning between analog and digital resulting in optimum system cost and performance for a .13 /spl mu/m CMOS process.
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