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This work introduces a universal Quantum-Dot Cellular Automata logic gate (UQCALG) for synthesizing symmetric functions with the target to reduce wire crossings in a design as well as the number of operating clock cycles. It is realized with the coupled majority-minority gate (CMVMIN) structure. The proposed UQCALG structure not only improves performance of(More)
This work reports a high speed protocol verificaion logic for Chip Multiprocessors (CMPs) realizing directory based cache coherence system. A special class of cellular automata (CA) referred to as single length cycle 2-attractor CA (TACA), has been introduced to identify the inconsistencies in cache line states of processors private caches. The introduction(More)