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This work reports an efficient solution for reaching agreement (consensus) among the processes of a distributed system. The better efficiency is achieved through early disposal of faulty processes while approaching for a consensus. The introduced network partitioning scheme further facilitates the progress by reducing the message exchange overhead.(More)
This work introduces a universal Quantum-Dot Cellular Automata logic gate (UQCALG) for synthesizing symmetric functions with the target to reduce wire crossings in a design as well as the number of operating clock cycles. It is realized with the coupled majority-minority gate (CMVMIN) structure. The proposed UQCALG structure not only improves performance of(More)
Synthesis of efficient DFT (Design for Testability) logic is of prime importance in robustly testable design of QCA based logic circuits. An ingenious universal QCA gate structure, Coupled Majority-Minority (CMVMIN) gate, realizes majority and minority functions simultaneously in its 2-outputs. This device enables area saving implementation of complex QCA(More)
The data coherence in the cache systems of CMPs with thousands of processors are to be more accurate and reliable. This work proposes an effective solution to address this issue through introduction of highly efficient test logic with the cache controller. It is based on the modular structure of Cellular Automata (CA) and a special class of CA referred to(More)
This work proposes a testable QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the Coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The characterization of defects in(More)
This work proposes a novel 4-state cache coherence protocol that ensures better efficiency in Chip Multiprocessors (CMPs) compared to that of conventional 4 and 5-state protocols, e.g. MESI/MOESI. The proposed MASI coherence protocol realizes judicious cache line state transition that has considerable impact on the reduction in number of data block(More)