Makoto Yabuuchi

Suggest Changes
Learn More
We discuss dynamic read and write stabilities of embedded SRAMs in 28-nm high-k/metal-gate (HK/MG) bulk CMOS technology. Test chips which include 1-Mbit single-port SRAM and 512-kbit dual-port SRAM(More)
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to(More)