Majid Rezazadeh

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Aknowledgement Hereby, we would like to appreciate the efforts of Working Group on IRIran 2010 UNGASS report. The members of this working group are as follows(in alphabetical order): We also would like to appreciate the efforts of the individuals who have participated in preparation of this report (such as data collection, technical assistance, revision of(More)
PURPOSE To assess the prevalence and associated factors of unprotected anal intercourse among Iranian male heterosexual Intra-Venous Drug Users (IDUs). METHODS In a cross-sectional study 360 male heterosexual IDUs were sampled from streets of eight different geographical parts of Iran. Variables such as socio-demographics, HIV knowledge (10 items), and(More)
BACKGROUND There is a large controversy in the literature about the inter-relations between perceived risk, knowledge, and risk behavior in different settings, and people at HIV risk are not an exception. AIM To assess additive and multiplicative effect of perceived HIV risk and HIV knowledge on sexual risk behavior of Injecting Drug Users (IDUs). (More)
In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for an NoC(More)
Introduction: Given the important role of family in shaping human behavior, the current research has been conducted with the aim of identifying the family characteristics of individuals with risky sexual behaviors. Materials and Methods: In this correlative study the statistical population included women with risky and extramarital sexual behaviors. 104(More)
A Multi-stage Interconnection Network (MIN) is one of the choices for Networks-on-Chip (NoCs) architecture designer for its simple topology and easy scalability with low degree. The evolution of digital design lies in the ability to shrink circuit size with each advance in process technology. As CMOS implementing technology continues to scale down, standard(More)
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