Majid Rahimi Nasab

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we propose a combination of Fat-Tree topology and Bisection routing in MPLS network-on-chip which can increase Communication load and quality of service which is suitable for multimedia applications. We compare the performance of IP and MPLS Fat-Tree-based Network-on-chips. The simulations of the architectures are done with two-dimensional Fat-Tree(More)
As CMOS technology scales down into the deep submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. We propose a combination of a topology and Multi-path routing which can increase fault-Tolerant and Communication(More)
we propose a combination of Mesh topology and Bisection routing in MPLS and IP network-on-chip which can increase Communication load with quality of service which is suitable for multimedia applications. We compare the performance of 2d-Mesh architectures in the sense of on chip network design methodology. The simulations of the architectures are done with(More)
In this paper, we discuss the difficulties Reserved Bandwidth Mechanisms for networks-on-chip by MPLS packet-forwarding technologies. Then, we compare these mechanisms in Network-On-Chip that is based on applying the well-known MPLS technology of large-scale computer networks to the on-chip environment. The NS-2 network simulator is used to evaluate the(More)
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