Majid Eslami Farsani

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
In this paper a structure for Differential Static CMOS Logic (DSCL) is proposed which uses two embedded transistors in a differential circuit. This structure introduces many modifications including Delay, Power, Power-delay-product (PDP), transient output current, time constant of circuit and outputs symmetry. The undesirable factors in Differential CMOS(More)
In this paper, a new coupling circuit is presented. This circuit uses a new method of subthreshold region biasing to decrease the value of coupling capacitor. In proposed circuit the Coupling capacitor is decreased about 98% in comparison with the ordinary capacitive coupling circuit. In addition, the proposed coupling circuit achieves higher linearity. The(More)
  • 1