Majed Valad Beigi

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3D integration enables large last level caches (LLCs) to be stacked onto a die. In addition, emerging Non Volatile Memories (NVMs) such as Spin-Torque Transfer RAM (STT-RAM) have been explored as a replacement for traditional SRAM-based LLCs due to their higher density and lower leakage power. In this paper, we aim to use the benefits of the integration of(More)
In this work, we develop a 3D architecture that utilizes STT-RAM for the last level cache (LLC). 3D integration enables large LLCs to be stacked onto a die. However, 3D architectures suffer from higher operating temperatures due to increased power densities. The elevated temperatures can adversely impact the STT-RAM performance and reliability. The(More)
In this paper, we introduce MIN, a novel method for assigning wavelengths to nodes dynamically on a nanophotonic network to minimize the impact of process variations (PVs). Among the available wavelengths on a waveguide, a subset of them, called bubbles, are left intentionally unused. These bubbles are then borrowed by nodes dynamically to improve the(More)
Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. The main challenge is avoiding deadlock anomalies while keeping limitations on packet injection and forwarding minimal. Current approaches which have a high complexity and as a result have a limited practical(More)
In this paper, we introduce Therma, a thermal-aware run-time thread migration mechanism for managing temperature fluctuations in nanophotonic networks. Nanophotonics is one of the most promising communication substrate candidates for next-generation high-performance systems. However, their underlying components are sensitive to temperature fluctuations.(More)
The move towards nanoscale Integrated Circuits (ICs) increases performance and capacity, but poses process variation and reliability challenges which may cause several faults on routers in Networks-on-Chips (NoCs). While utilizing healthy routers in an NoC is desirable, faulty regions with different shapes are formed gathering faulty routers. Fault regions(More)
Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. The main challenge is avoiding deadlock anomalies while keeping limitations on message injection and forwarding minimal. Current approaches, whose complexity is so high that their practical applicability is limited,(More)
Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient(More)
The routing algorithms for parallel computers, on-chip networks, multi-core processors, and multiprocessors system-on-chip (MP-SoCs) exhibit router failures must be able to handle interconnect router failures that render a symmetrical mesh non-symmetrically. When developing a routing methodology, the time complexity of calculation should be minimal, and(More)
This paper presents a novel methodology to provide a promising solution for complex on-chip communication problems in order to reduce power consumption and delay. Our proposed reconfigurable Network-on-Chip (NoC) architecture is integrated with the radio frequency Interconnect (RF-I) with signal propagation at the speed of light. It is based on setting up(More)
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