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Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. Recently, a new language, SystemVerilog, was introduced and became an IEEE standard. SystemVerilog extends the hardware description language Verilog by including higher(More)
iii ACKNOWLEDGEMENTS So many faculty members, persons, and students helped and influenced my work at Southern Methodist University. First, I gratefully acknowledge Dr. Mitchell A. Thornton, my dissertation advisor, for his guidance, encouragement and support throughout the research phase of this dissertation. Without him, I would not have been able to(More)
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