Mahmoud Reza Ahmadi

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—This paper presents a pilot-based clock and data recovery CDR technique for high-speed serial link applications where a low-amplitude bitrate clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection locked oscillator and is used to drive the receiver front-end samplers. The performance of(More)
—This paper presents an architecture and an optimization framework that uses partial response (PR) equalization for high-speed links. PR equalization is achieved through a combined use of linear transmit equalization and decision feedback equalization (DFE). This technique outperforms full-channel/impulse equalization for a wide range of channels in(More)
— This paper presents the design of a 12 Gbps multi-lane 2 31 − 1 pseudo-random binary sequence (PRBS) generator in 0.18 µm TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to the fT of the process. In order to operate at frequencies higher than the limit imposed by the fT of the PMOS devices, the PRBS(More)
—A low-power, three-lane, 2 31 1 pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-m CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been(More)
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