Mahmoud Elassal

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This paper presents an architectural analysis for MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and(More)
In this paper we present low power maximum a posteriori (MAP) decoder architectures using dual supply voltages. The architecture leverages an application specific integrated circuits (ASIC) structure, where the architecture components that require a higher performance are powered from a high supply voltages V/sub ddH/, and the less demanding components are(More)
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