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The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This(More)
The gate leakage current present in double-gate fully depleted fin-shaped MOSFETs with metal gate/single oxynitride layer is modeled. It can significantly contribute to the drive current measured in different conditions, according to its dependence on applied voltages to the structure electrodes, as well as, on the Si regions where the gate has control.(More)
Wide band gap materials like LiF are being used as electron/injection layers (EIL/ETL) in PLEDs, to improve their efficiency. Recently, another wide gap material, TiOx, is being studied as an alternative for these EIL/ETL layers. TiOx layers are also studied as optical spacer for PSCs. In this work, TiOx layers of different thickness were deposited by spin(More)
This paper presents the expressions and procedure for precise and simple modeling of the subthreshold region of OTFTs. The total drain current in the OTFT is calculated as the sum of two components, one calculated in above threshold regime plus the one corresponding to the below threshold regime. The tanh function is used to sew both regions. Good agreement(More)
In this work we present a procedure for modeling the characteristics of amorphous oxide semiconductor TFTs, including the hump observed in the transfer characteristics after DC stress. It is based on the Universal Method and Extraction Procedure, UMEM, previously applied to other types of TFTs. The compact model and extraction procedure allows determining(More)
The presence of a deformation or hump in the subthreshold region of the transfer characteristic of Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) has been observed after DC stress and related to different causes. In previous works, it has been shown that in devices with active-layer thickness greater than 120 nm, a region with relatively(More)
During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO 2 films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason,(More)
SUMMARY Recently we developed a model for symmetric double-gate MOSFETs (SDDGM) that, for the first time, considers the doping concentration in the Si film in the complete range from 1 Â 10 14 to 3 Â 10 18 cm À3. The model covers a wide range of technological parameters and includes short channel effects. It was validated for different devices using data(More)
Polymeric solar cells have attracted much attention during the last years due to their lower fabrication cost and possibility of using flexible substrates. However, their efficiency is usually less than 5%. Among factors affecting polymeric solar cells efficiency, the active layer morphology related to blend preparation and annealing, is one of the most(More)