Madhavan Swaminathan

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This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium® 4 microprocessor. These values imply(More)
A fast and accurate layout-level synthesis and optimization technique for embedded passive RF components and circuits such as inductors and bandpass filters have been presented. The filters are composed of embedded inductors and capacitors in a multilayer liquid crystalline polymer substrate. The proposed approach is based on a combination of segmented(More)
Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose(More)
This paper presents for the first time the design, implementation, measurements, reliability data and integration of multiple RF components such as filters, baluns, diplexers, and a combination of the above on Liquid Crystalline Polymer (LCP) based substrates for communication standards such as 802.11 a/b/g, LMDWMMDS, sa1,ellitddigital TV, UWB, cellular and(More)
New dielectric materials are being used for reducing electromagnetic interference (EMI) and improving signal integrity (SI). Examples include using high dielectric constant materials for decoupling and thin dielectrics for managing return currents. As the frequency of the signals being propagated through such materials increases, the frequency dependent(More)
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the microarchitectural impact of using multiple PLLs for clock distribution. Two PLL phase(More)
This paper describes a methodology for performing system level signal and power integrity analyses of SiP-based systems. The paper briefly outlines some new modeling and simulation techniques that have been developed to enable the proposed methodology. Some results based on the application of this methodology on test systems are also presented.