This paper proposes a novel self-healing methodology for embedded RF Amplifiers (LNAs) in RF sub-systems. The proposed methodology is based on oscillation principles in which the Device-under-Test (DUT) itself generates the output test signature with the help of additional circuitry. The self-generated test signature from the DUT is analyzed by using… (More)
—Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose… (More)
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little… (More)
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase… (More)
Nanocomposite and nanolayered dielectrics provide new avenues to enhance the performance of RF and power components. They enable engineering of properties such as permeability, permittivity, fr equency and temperature-stability, and tunability, along with low loss, to miniaturize next-generation multiband RF modules that require higher fu nctional density… (More)
— Causality, which deals with the precise timing of signal propagation through passive structures like interconnects, is an important problem in the time domain simulation of distributed passive networks. If unaccounted for, it can lead to significant error in the signal integrity analysis of high-speed digital systems. Distributed passive systems are… (More)
Abstracl In this work, we present an automatic module placement algorithm for simultaneous power supply noise and routing congestion minimization for 3D packaging. We employ decoupling capacitance insertion for noise suppression and 3D global routing for congestion avoidance.